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Please use this identifier to cite or link to this item: http://ir.lib.stu.edu.tw:80/ir/handle/310903100/2903

Title: 10位元100M Sa/s電流導向式數位類比轉換器
A 10-bit 100M Sa/s Current-Steering Digital-to-Analog Converter
Authors: 林建周
Chien-Chou Lin
Contributors: 電腦與通訊系碩士班
鄭國華
Keywords: 電流導向式;電流式;數位類比轉換器;DAC
Current-steering;Current type;Digital to Analog converter;DAC
Date: 2012
Issue Date: 2012-03-22 15:26:51 (UTC+8)
Publisher: 高雄市:[樹德科技大學電腦與通訊系碩士班]
Abstract: 本論文設計實現一個應用於10位元100M Sa/s電流導向式數位類比轉換器,在數位類比轉換器電路的實現,使用TSMC 0.35um 2P4M mixed signal CMOS製程。
模擬結果顯示,DAC微分非線性度的測試結果在±0.5(LSB)、積分非線性度誤差其值小於0.3(LSB)、穩定時間為6nS、功率消耗為99.33mW,面積1.1mm2,在此架構中,最大有六個有效數位碼轉成溫度計碼後,控制63個電流源,最小四個有效數位碼使用二進位權重碼,控制4個電流源,利用此架構可以改善數位類比轉換器的微分非線性誤差,突波、確保電路單調性。
在實際結果方面,依照CIC類比量測系統量測,並利用電流源簡單縮小化,10位元100M Sa/s電流導向式數位類比轉換器模擬結果為:DNL小於1( LSB)、INL小於3 (LSB)、當輸入正弦波為20MSa/s時,則SFDR為34dB。整體方面最大的消耗功率為95mW、佈局面積為1.1mm2。
In this thesis, a 10-bit 100MSa/s current-steering digital-to-analog converter is implemented using TSMC 0.35um 2P4M mixed signal CMOS technology.
The DAC adopts the segmented architecture which comprises a segment of 6-bit into 63 equally weighted current sources in the MSB and a segment of 4-bit binary-weighted current source in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture.
The DAC is simulated by CIC using Analog Measurement System. The proposed DAC has the following performances: The sampling rate of DAC is 100M S/a, INL is less then 0.3LSB, DNL is less than ±0.5LSB, setting time is 6nS, for 20MSa/s sine wave input the SFDR is 34dB.
The power consumption is 99.33mW at the maximum conversion rate and total area is 1.1 mm2.
Appears in Collections:[電腦與通訊系(所)] 博碩士論文

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