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Title: CMOS積體電路與混成電路之射頻低雜訊放大器設計與製作
Design and Implementation of Low Noise Amplifier Using CMOS and Hybrid Technology
Authors: 張庭端
Ting-Duan Chang
Contributors: Wu-Nan Chen
電腦與通訊研究所
Keywords: 低雜訊放大器
LNA
Date: 2007
Issue Date: 2011-05-24 14:35:36 (UTC+8)
Publisher: 高雄市:[樹德科技大學電腦與通訊研究所]
Abstract: 本論文包含被動元件之濾波器設計與主動低雜訊放大器電路之設計,濾波器設計利用缺陷型結構,作成符合IEEE 802.15.3a之寬頻濾波器,在低雜訊放大器使用電晶體(FET)混成微波積體電路及金屬氧化半導體(CMOS)來製作射頻低雜訊放大器。
寬頻濾波器,上層採用平行偶合形式,下層則利用缺陷型接地結構來產生寬頻濾波器其頻寬為(3-5GHz)。在混成低雜訊放大器電路使用FET(NEC32584C)電晶體為共源極(CS)架構應用於5.2GHz量測出具良好特性其增益為14.2dB,雜訊指數為2.8dB。在CMOS電路採用台灣積體電路(TSMC)0.18μm製程設計低雜訊放大器採疊接 (Cascode)電路架構應用於10GHz的X頻帶,消耗功率為18.9mW,增益為16.1dB,具有極低的雜訊指數為2.3dB。和製作另一個可控制38GHz低雜訊放大器採用串接(Cascade)5極電路架構應用於LMDS系統,消耗功率為18.4 mW,增益為17.5dB,雜訊指數為4.9dB,其可控制增益其應用於第二種規格。
This thesis contains passive filter and active low noise amplifiers. In passive filter design, defect ground structure (DGS) is utilized for wide band application for IEEE 802.15.3a. In low noise amplifiers, the FET hybrid microwave integrated circuit was implemented for 802.16 and two CMOS process LNA were designed for millimeter wave application.
The proposed wide band bandpass filter employs a microstrip parallel couple on the upper metal layer and DGS on the bottom layer, which can produce passband of 3-5GHz. In hybrid low noise amplifier integrated circuit, FET (NEC32584C transistor) applying common source configuration is exploited for 5.2GHz center frequency. The performance includes measured power gain 14.2 dB and noise figure 2.8 dB. A cascade LNA operated at 10GHz for X band application was realized in TSMC 0.18-μm process. The simulation characteristics contains power consumption 18.9 mW, power gain 16.1 dB and low noise figure of 2.3 dB. The other CMOS LNA was designed at 38GHz using five-pole Cascade technology, which possesses additional gain control function. This low noise amplifier for LMDS application features power consumption of 18.4 mW, power gain of 17.5dB and noise figure of 4.9 dB.
Appears in Collections:[電腦與通訊系(所)] 博碩士論文

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